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FEATURED POST

Recent Posts

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Hi, my name is Shimon Cohen and I am a verification, analog and Mixed-Signal engineer working for over 2 decades in the IC industry.

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The focus of this blog will revolve around UVM, SV and SV-RNM 

Why I started this blog

I'm enthusiastic about diving deeper into  the UVM framework and the SystemVerilog (SV) language, particularly constructs that I haven't had the opportunity to explore extensively (yet).

 

To create a central repository for my experiments and make them readily accessible, I decided to establish this platform.

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As a novice engineer, I relied heavily on content from fellow bloggers and various forums to acquire knowledge. Contributing back is one of the foremost objectives of this blog, if not the most crucial.

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Moreover, I believe in the power of sharing and receiving feedback from our community, so why not create a space for that?

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What can you anticipate finding here?

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  1. In-depth exploration and analysis of intriguing posts from fellow bloggers or forum sites, where I will provide examples and add my own insights.

  2. Challenges I've successfully tackled in my daily work that I find both interesting and worthy of documentation.

  3. Ongoing experiments with SystemVerilog Real Number Modeling (SV-RNM) models.

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I look forward to sharing this journey with you and fostering a vibrant exchange of ideas and experiences.

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