RAIN OF `UVM_INFO(S)

Hello, my name is Shimon Cohen.

​

I have been working in the IC (Integrated Circuit) industry for over two decades.

During the initial phase of my career, I specialized in analog circuit design, primarily focusing on power management ICs.

Additionally, I was involved in modeling mixed-signal system behavior using Verilog-A and Verilog-AMS languages.

​

In the latter part of my career, I had the opportunity to expand my skill set by learning SystemVerilog (SV) and Universal Verification Methodology (UVM), marking the beginning of my journey in digital verification.

​

Recently, I have delved into SV-RNM (SystemVerilog Real Number Modeling) experiments with the aim of enhancing our regression testing capabilities, ultimately ensuring the comprehensive verification of the entire system.

​