Embarking on the journey of UVM (Universal Verification Methodology) verification is an exciting yet challenging endeavor for many engineers and enthusiasts in the field of hardware design and verification. As someone deeply immersed in the world of UVM, I understand the importance of having reliable and diverse resources to guide you through this intricate landscape.
In this blog post, I aim to share my own learning experience and provide a organized list of invaluable sources that have significantly contributed to my understanding of UVM verification. Whether you're a novice seeking a starting point or an experienced professional looking to deepen your knowledge, this guide is crafted to help you navigate through a multitude of resources, including books, blogs, online platforms, vendor websites, and more.
I'm constantly on the lookout for new learning resources. Please feel free to leave a comment if you have any suggestions for me.
Books:
The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology. The initial book in my UVM learning journey was authored by Ray Salemi. I acquired this book when my knowledge of UVM was minimal, and I had only a basic understanding of logic design. Ray Salemi's work proved immensely beneficial, providing me with a clear grasp of UVM and its fundamental components.
SystemVerilog for Verification 3rd ed. 2012 Edition. An essential read authored by Chris Spear and Greg Tumbush, this book encompasses all the features of test bench language, using a comprehensive ATM router verification environment as an illustrative example.
SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling. While I typically focus on verification rather than crafting hardware and design models, I believe that obtaining a comprehensive understanding of the subject requires some familiarity with RTL modeling techniques. In my opinion, the book by Stuart Sutherland, Simon Davidmann, and Peter Flake is an excellent resource for learning hardware modeling. It not only serves as a valuable guide but also features a model for an ATM router, enhancing the learning experience.
Universal Verification Methodology UVM Cookbook. No need for further explanation. it's evident that this is the go-to book for every verification engineer, downloaded and revisited countless times since entering the field. You'll always find me with this book open on my computer during my daily work.
Coverage Cookbook from website "The Coverage Cookbook describes the different types of coverage that are available to keep track of the progress of the verification process, how to create a functional coverage model from a specification, and provides examples of how to implement functional coverage for different types of designs."
SystemVerilog Assertions and Functional Coverage Ashok B. Mehta's book contains numerous examples and diagrams, along with waveform plots.
Sites:
Siemens Verification Academy No need for further explanation. Everything essential for a verification engineer, including publications, courses, forums, and more, is available here.
Cadence Learning and Support Free online courses covering most, if not all, topics related to the integrated circuit industry.
Chip Verify I invested a significant number of hours on this website as a beginner, and it greatly assisted me when I embarked on my journey.
ClueLogic If you're a fan of sweets and interested in learning UVM, this is the place to visit.
Verification Guide SV and UVM tutorials with many examples
VLSI Verify SV and UVM tutorials, I learned UVM callbacks using this site
Learn UVM verification Articles, blog and more
SystemVerilog Style Guide A style guide for SystemVerilog code
YouTube:
The webinar titled 'The Finer Point of UVM Sequences' presented by John Aynsley from Doulos, provides valuable insights into the workings of UVM sequences, including their handshake mechanism with sequencers and drivers. I constructed a comprehensive verification environment, drawing inspiration from the layered sequences section featured in this webinar's tutorials.
Blogs:
Verification Gentlemen Blog Blog by Tudor Timi, I believe this blog stands out as one of the most widely read in the field. One particular post focusing on burst communication served as the foundation for the communication protocol agent I've incorporated into numerous projects since then.
Ten Thousand Failures Blog by Eldon Nelson, Very interesting posts in many case also come with github repositories.
AMIQ Consulting The blog posts are thoroughly elucidated, complemented by the inclusion of diagrams and waveform plots.
Verification Excellence Found this blog not long ago, looks like interesting posts.
Verilab Insights Top-notch papers on SystemVerilog and UVM, with one of my favorites being "Reactive Slaves."
sunburst-design Well-crafted publications covering a variety of UVM topics.
dvtalk A blog by Hung Nguyen Viet that features various SystemVerilog (SV) and Universal Verification Methodology (UVM) experiments conducted by this experienced DV professional.
Posts:
System Verilog Macro: A powerful Feature Feature for Design Verification Projects Excellent post about how to build sv macros
Functional Coverage Patterns: Bitwise Coverage Functional Coverage Patterns: The Counter How to Ignore Coverage Bins Using Expressions in SystemVerilog These three posts by Amiq showcase various techniques for gathering coverages in SystemVerilog. I gained a lot of valuable insights from these posts, and some of the techniques were entirely new to me.
Papers (I read many but these I like the most):
Mastering Reactive Slaves in UVM (google it) A paper by Mark Litterick, Jeff Montesano and Taruna Reddy about how to build reactive slaves (responders) in UVM.
SystemVerilog Constraint Layering via Reusable Randomization Policy Classes I wrote a post based on this paper, really amazing topic.
Parameterized Classes Interfaces & registers I find the subject of parametrization in SystemVerilog to be quite intricate. This paper greatly assisted me in comprehending it. Interestingly, one of the tips it offers is "Avoid parametrization if possible."
Conferences:
References/LRM: